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| author | Marc Zyngier <[email protected]> | 2022-07-20 15:26:05 +0100 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2022-07-20 15:26:05 +0100 |
| commit | 0fa72ed05ebf15323047219e56bb7effbd2d506a (patch) | |
| tree | 7e1f7c747164475b418f544ed73407b508dab0c9 /net/openvswitch/flow.c | |
| parent | 2b0d7ab1646c371268ff0435b6330ba4b45a97f0 (diff) | |
| parent | e8bba72b396cef7c919c73710f3c5884521adb4e (diff) | |
Merge branch irq/loongarch into irq/irqchip-next
* irq/loongarch:
: .
: Merge the long awaited IRQ support for the LoongArch architecture.
:
: From the cover letter:
:
: "Currently, LoongArch based processors (e.g. Loongson-3A5000)
: can only work together with LS7A chipsets. The irq chips in
: LoongArch computers include CPUINTC (CPU Core Interrupt
: Controller), LIOINTC (Legacy I/O Interrupt Controller),
: EIOINTC (Extended I/O Interrupt Controller), PCH-PIC (Main
: Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt
: Controller in LS7A chipset) and PCH-MSI (MSI Interrupt Controller)."
:
: Note that this comes with non-official, arch private ACPICA
: definitions until the official ACPICA update is realeased.
: .
irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
irqchip: Add LoongArch CPU interrupt controller support
irqchip: Add Loongson Extended I/O interrupt controller support
irqchip/loongson-liointc: Add ACPI init support
irqchip/loongson-pch-msi: Add ACPI init support
irqchip/loongson-pch-pic: Add ACPI init support
irqchip: Add Loongson PCH LPC controller support
LoongArch: Prepare to support multiple pch-pic and pch-msi irqdomain
LoongArch: Use ACPI_GENERIC_GSI for gsi handling
genirq/generic_chip: Export irq_unmap_generic_chip
ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
APCI: irq: Add support for multiple GSI domains
LoongArch: Provisionally add ACPICA data structures
Signed-off-by: Marc Zyngier <[email protected]>
Diffstat (limited to 'net/openvswitch/flow.c')
0 files changed, 0 insertions, 0 deletions