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authorClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>2023-10-10 16:26:57 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2023-10-12 20:05:52 +0200
commit4bce4bedbe6daa54cf701184601f913a0c00bb1c (patch)
tree0c9f96ba77b1edf1eafbc7ca21b1bd4248c17146 /net/mptcp/crypto_test.c
parentfd627207aaa782c1fd4224076b56a03a1059f516 (diff)
clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2
Add clock and reset support for the SDHI1 and SDHI2 blocks on the RZ/G3S (R9A08G045) SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231010132701.1658737-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'net/mptcp/crypto_test.c')
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