diff options
| author | Patrik John <[email protected]> | 2021-11-23 14:27:38 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2021-11-25 18:26:32 +0100 |
| commit | b40de7469ef135161c80af0e8c462298cc5dac00 (patch) | |
| tree | aa13e472cbfa2ebd11e1f2dacd5da0a90cf98f47 /net/lapb/lapb_timer.c | |
| parent | 0b993fc1fec7b43a75b875763dc58c5940eea47a (diff) | |
serial: tegra: Change lower tolerance baud rate limit for tegra20 and tegra30
The current implementation uses 0 as lower limit for the baud rate
tolerance for tegra20 and tegra30 chips which causes isses on UART
initialization as soon as baud rate clock is lower than required even
when within the standard UART tolerance of +/- 4%.
This fix aligns the implementation with the initial commit description
of +/- 4% tolerance for tegra chips other than tegra186 and
tegra194.
Fixes: d781ec21bae6 ("serial: tegra: report clk rate errors")
Cc: stable <[email protected]>
Signed-off-by: Patrik John <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'net/lapb/lapb_timer.c')
0 files changed, 0 insertions, 0 deletions