diff options
| author | Nishanth Menon <[email protected]> | 2022-02-15 14:10:08 -0600 |
|---|---|---|
| committer | Nishanth Menon <[email protected]> | 2022-02-22 11:04:12 -0600 |
| commit | a966803781fc5e1875511db9392b0d16174c5dd2 (patch) | |
| tree | bb888d0f663382655ba8d2e745b7e2e72e78afbd /net/lapb/lapb_timer.c | |
| parent | de60edf1be3d42d4a1b303b41c7c53b2f865726e (diff) | |
arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/[email protected]/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438
Cc: [email protected]
Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
Reported-by: Marc Zyngier <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'net/lapb/lapb_timer.c')
0 files changed, 0 insertions, 0 deletions