ARM: 7752/1: errata: LoUIS bit field in CLIDR register is incorrect

On Cortex-A9 before version r1p0, the LoUIS bit field of the CLIDR
register returns zero when it should return one. This leads to cache
maintenance operations which rely on this value to not function as
intended, causing data corruption.

The workaround for this errata is to detect affected CPUs and correct
the LoUIS value read.

Acked-by: Will Deacon <[email protected]>
Acked-by: Nicolas Pitre <[email protected]>
Cc: [email protected]
Signed-off-by: Jon Medhurst <[email protected]>
Signed-off-by: Russell King <[email protected]>

0 files changed, 0 insertions, 0 deletions