diff options
| author | H. Peter Anvin (Intel) <[email protected]> | 2023-12-05 02:49:55 -0800 |
|---|---|---|
| committer | Thomas Gleixner <[email protected]> | 2024-01-25 19:10:30 +0100 |
| commit | 51c158f7aaccc6f6423a61a1df4a0d4c0d9d22a9 (patch) | |
| tree | c7fd3310169d737a4686f7abd564841ee5b4a126 /net/lapb/lapb_timer.c | |
| parent | 2cce95918d635126098d784c040b59333c464b20 (diff) | |
x86/cpufeatures: Add the CPU feature bit for FRED
Any FRED enabled CPU will always have the following features as its
baseline:
1) LKGS, load attributes of the GS segment but the base address into
the IA32_KERNEL_GS_BASE MSR instead of the GS segment’s descriptor
cache.
2) WRMSRNS, non-serializing WRMSR for faster MSR writes.
Signed-off-by: H. Peter Anvin (Intel) <[email protected]>
Signed-off-by: Xin Li <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Tested-by: Shan Kang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'net/lapb/lapb_timer.c')
0 files changed, 0 insertions, 0 deletions