diff options
| author | Michael Williamson <[email protected]> | 2011-05-20 10:26:06 -0400 |
|---|---|---|
| committer | Liam Girdwood <[email protected]> | 2011-05-21 12:07:56 +0100 |
| commit | 2aba76f014a7b56ab4fe75845c5fd57b5590acc2 (patch) | |
| tree | 67cd2be68adce646b25b74e6e52bb6cc4f25f6c7 /net/lapb/lapb_timer.c | |
| parent | 4a787a3ff3f419c23ab0a5cef677fa441356b818 (diff) | |
audio: tlv320aic26: fix PLL register configuration
The current PLL configuration code for the tlc320aic26 codec appears to assume a
hardcoded system clock of 12 MHz. Use the clock value provided by the DAI_OPS
API for the calculation.
Tested using a MityDSP-L138 platform providing a 24.576 MHz clock.
Signed-off-by: Michael Williamson <[email protected]>
Acked-by: Mark Brown <[email protected]>
Signed-off-by: Liam Girdwood <[email protected]>
Diffstat (limited to 'net/lapb/lapb_timer.c')
0 files changed, 0 insertions, 0 deletions