diff options
| author | Clint Taylor <[email protected]> | 2014-09-30 10:30:22 -0700 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2014-10-01 10:01:41 +0200 |
| commit | ebb69c95175609990af708ec90c46530f5a2c819 (patch) | |
| tree | fc400e341f316ec24c2db3b9a49e38338a043024 /net/lapb/lapb_subr.c | |
| parent | 67956867aa07c59d6d83628bbc9ee4bd9799a1e1 (diff) | |
drm/i915: Enable pixel replicated modes on BDW and HSW.
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write
to the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing
to the DPLL only double the pixel clock.
ver2: Macro name change from MULTIPLY to PIPE_MULTI. (Daniel)
ver3: Do not set pixel multiplier if transcoder is eDP (Ville)
ver4: Macro name change to PIPE_MULT and default else pixel_multiplier
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <[email protected]>
Cc: Daniel Vetter <[email protected]>
Cc: Jani Nikula <[email protected]>
Signed-off-by: Clint Taylor <[email protected]>
Reviewed-by: Ville Syrjälä <[email protected]>
[danvet: Appease checkpatch and move one hunk back into the right
place that git am misplace!?]
Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'net/lapb/lapb_subr.c')
0 files changed, 0 insertions, 0 deletions