diff options
| author | AngeloGioacchino Del Regno <[email protected]> | 2023-03-01 10:55:12 +0100 |
|---|---|---|
| committer | Matthias Brugger <[email protected]> | 2023-03-30 09:47:08 +0200 |
| commit | 61348fe9e75b7edb25b26ce789a9aec617b20090 (patch) | |
| tree | 1cf5fb74a542bea025d964acc778fb4c8bc7f372 /net/lapb/lapb_subr.c | |
| parent | e12333451e76e1fe9121a3ce30b930c719fc04dd (diff) | |
arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain
The mfg_ref_sel clock is a mux used to switch between different "safe"
(and slower) clock sources for the GPU: this is used during MFGPLL
reconfiguration and eventually during idling at very low frequencies.
This clock getting turned off means that the GPU will occasionally be
unclocked, producing obvious consequences such as system crash or
unpredictable behavior: assigning it to the top level MFG power domain
will make sure that this stays on at all times during any operation on
the MFG domain (only GPU-related transactions).
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Matthias Brugger <[email protected]>
Diffstat (limited to 'net/lapb/lapb_subr.c')
0 files changed, 0 insertions, 0 deletions