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authorOlav Haugan <[email protected]>2014-08-04 19:01:02 +0100
committerWill Deacon <[email protected]>2014-09-01 16:48:56 +0100
commit1fc870c7efa364862c3bc792cfbdb38afea26742 (patch)
tree1c5719e57b7fccba898486eb622027036ee770a2 /net/lapb/lapb_subr.c
parenta18037b27ebd23edf5edad8bc6ceb72e4bb5716d (diff)
iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1
Stage-1 context banks do not have the SMMU_CBn_TCR[SL0] field since it is only applicable to stage-2 context banks. This patch ensures that we don't set the reserved TCR bits for stage-1 translations. Cc: <[email protected]> Signed-off-by: Olav Haugan <[email protected]> Signed-off-by: Will Deacon <[email protected]>
Diffstat (limited to 'net/lapb/lapb_subr.c')
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