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authorNishanth Menon <[email protected]>2021-11-12 22:26:40 -0600
committerVignesh Raghavendra <[email protected]>2021-12-03 17:21:36 +0530
commita172c86931709d6663318609d71a811333bdf4b0 (patch)
tree11399d12f913c25349039e9e7d2c05f0f86114a3 /net/lapb/lapb_out.c
parente9ba3a5bc6fdc2c796c69fdaf5ed6c9957cf9f9d (diff)
arm64: dts: ti: k3-j7200: Correct the d-cache-sets info
A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache - ICache is 3-way set-associative - Dcache is 2-way set-associative - Line size are 64bytes 32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways 512 ways / 2 (Dcache is 2-way per set) = 256 sets. So, correct the d-cache-sets info. [1] https://www.ti.com/lit/pdf/spruiu1 Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Peng Fan <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Pratyush Yadav <[email protected]> Reviewed-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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