diff options
author | Linus Walleij <[email protected]> | 2022-03-17 23:58:43 +0100 |
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committer | Rob Herring <[email protected]> | 2022-03-20 15:02:22 -0400 |
commit | 094b10cb795a85e2f90f03c24b030888ab2f1fa3 (patch) | |
tree | 8621e0463425811c396b822a35285de35ff54d20 /net/lapb/lapb_in.c | |
parent | 5505409e423f61c981d84f53dee2a93bf3ba5913 (diff) |
dt-bindings: gnss: Add two more chips
The CSR GSD4t is a CSR product using the SiRFstarIV core, and
the CSR CSRG05TA03-ICJE-R is a CSR product using the SiRFstarV
core.
These chips have a SRESETN line that can be pulled low to hard
reset the chip and in some designs this is connected to a GPIO,
so add this as an optional property.
Update the example with a reset line so users see that it need
to be tagged as active low.
Cc: [email protected]
Cc: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'net/lapb/lapb_in.c')
0 files changed, 0 insertions, 0 deletions