diff options
| author | Tony Luck <[email protected]> | 2022-01-31 15:01:08 -0800 |
|---|---|---|
| committer | Borislav Petkov <[email protected]> | 2022-02-01 16:15:19 +0100 |
| commit | 00a2f23eef7d1fa6c2dfdc613857b84fbf5e2b3b (patch) | |
| tree | ab88738de6a22311e9bf260341b856e2845009bf /net/lapb/lapb_in.c | |
| parent | 0dcab41d3487acadf64d0667398e032341bd9918 (diff) | |
x86/cpu: X86_FEATURE_INTEL_PPIN finally has a CPUID bit
After nine generations of adding to model specific list of CPUs that
support PPIN (Protected Processor Inventory Number) Intel allocated
a CPUID bit to enumerate the MSRs.
CPUID(EAX=7, ECX=1).EBX bit 0 enumerates presence of MSR_PPIN_CTL and
MSR_PPIN. Add it to the "scattered" CPUID bits and add an entry to the
ppin_cpuids[] x86_match_cpu() array to catch Intel CPUs that implement
it.
Signed-off-by: Tony Luck <[email protected]>
Signed-off-by: Borislav Petkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'net/lapb/lapb_in.c')
0 files changed, 0 insertions, 0 deletions