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authorSimon Horman <horms+renesas@verge.net.au>2018-02-12 15:39:27 +0100
committerSimon Horman <horms+renesas@verge.net.au>2018-04-16 16:01:55 +0200
commitb1548238b2252199b7ea217abbc3d96b742c7e63 (patch)
tree660625461256b58850fadceb1f65c87e9d4478ed /mm
parentf8ce138029058fb7b144b866ae5cdb98db58f4fb (diff)
ARM: dts: r7s72100: add soc node
Add soc node to represent the bus and move all nodes with a base address into this node. This is consistent with handling of R-Car Gen3 and Gen2 SoCs in mainline. It is intended to migrate other Renesas ARM-based SoCs to this scheme. The ordering is derived from simply moving each node with an address up to before any nodes without a base address that occur before the soc node. To improve maintainability follow-up patches will sort subnodes of both the new soc node and the root node. This patch should not introduce any functional change. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'mm')
0 files changed, 0 insertions, 0 deletions