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authorMika Westerberg <mika.westerberg@linux.intel.com>2022-04-05 12:38:10 +0300
committerBjorn Helgaas <bhelgaas@google.com>2022-04-07 12:00:36 -0500
commit03038d84ace72678a9944524508f218a00377dc0 (patch)
tree6f6b832cbbb930485455325b803ed8c512b41ff8 /mm
parent3123109284176b1532874591f7c81f3837bbdc17 (diff)
PCI/ASPM: Make Intel DG2 L1 acceptable latency unlimited
Intel DG2 discrete graphics PCIe endpoints advertise L1 acceptable exit latency to be < 1us even though they can actually tolerate unlimited exit latencies just fine. Quirk the L1 acceptable exit latency for these endpoints to be unlimited so ASPM L1 can be enabled. [bhelgaas: use FIELD_GET/FIELD_PREP, wordsmith comment & commit log] Link: https://lore.kernel.org/r/20220405093810.76613-1-mika.westerberg@linux.intel.com Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'mm')
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