dt-bindings: mmc: arasan,sdci: Add gate property for Xilinx platforms

Add gate property in example node for Xilinx platforms which will be used
to ungate the DLL clock. DLL clock is required for higher frequencies like
50MHz, 100MHz and 200MHz.
DLL clock is automatically selected by the SD controller when the SD
output clock frequency is more than 25 MHz.

Signed-off-by: Swati Agarwal <[email protected]>
Co-developed-by: Sai Krishna Potthuri <[email protected]>
Signed-off-by: Sai Krishna Potthuri <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ulf Hansson <[email protected]>

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