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authorGeert Uytterhoeven <geert+renesas@glider.be>2017-10-12 11:35:12 +0200
committerSimon Horman <horms+renesas@verge.net.au>2017-10-16 11:41:41 +0200
commit60b672fe7e28358c1cffdab4724b203f6cf2901b (patch)
tree248fc0a7fab2d268b6dec74dc70d67039349530a /lib/timerqueue.c
parentaea0089ae8058a9bf4c9766f3208809fc28c99f0 (diff)
ARM: dts: r8a7791: Add missing clock for secondary CA15 CPU core
Currently only the primary CPU in the CA15 cluster has a clocks property, while the secondary CPU core is driven by the same clock. Add the missing clocks property to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'lib/timerqueue.c')
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