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authorGeert Uytterhoeven <geert+renesas@glider.be>2017-10-12 11:35:15 +0200
committerSimon Horman <horms+renesas@verge.net.au>2017-10-16 11:43:35 +0200
commit5614e69269232da1f378e5be92714b96cdb090ef (patch)
tree140c1b6f122131e5414c9d076495b6665b1bedeb /lib/timerqueue.c
parentf359fd3bba71176a122939fe3db9c7f20000d3f0 (diff)
ARM: dts: r8a7794: Add missing clock for secondary CA7 CPU core
Currently only the primary CPU in the CA7 cluster has a clocks property, while the secondary CPU core is driven by the same clock. Add the missing clocks property to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'lib/timerqueue.c')
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