diff options
| author | Jayachandran B <[email protected]> | 2015-12-18 15:12:03 +0530 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2016-01-10 12:19:01 +0000 |
| commit | 0c8ba9d28518822d612de23fc9020b2a66a0228c (patch) | |
| tree | 89295d33fcb50b73dba25302a9979fb013cf9cd0 /lib/timerqueue.c | |
| parent | 648e3a5bdddf8e7ad9c27450ac368b8bccd807a5 (diff) | |
ASoC: Intel: Skylake: fix reset controller sequencing
MISCBDCGE is a new register for Misc Backbone clock gate control
which is useful to control while resetting the link and ensuring
controller is in required state so add API to control it
HW recommends that we reset with CGCTL.MISCBDCGE disabled, so add
that while doing init chip and reset sequence.
Signed-off-by: Jayachandran B <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'lib/timerqueue.c')
0 files changed, 0 insertions, 0 deletions