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| author | Lad Prabhakar <[email protected]> | 2022-06-22 19:17:22 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2022-07-05 09:15:52 +0200 |
| commit | 668d361c9d893be3cbd4f3650e1934a62b204def (patch) | |
| tree | 7aa835f8fe6ccb0408d0a2b6337fa8f1a665a545 /lib/test_xarray.c | |
| parent | eb2789785428e2dbc3d5f413b16c67ff90d828c1 (diff) | |
dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions
Renesas RZ/Five SoC has almost the same clock structure compared to the
Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just
amend the RZ/Five CPG clock and reset definitions.
Signed-off-by: Lad Prabhakar <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'lib/test_xarray.c')
0 files changed, 0 insertions, 0 deletions