diff options
author | Michael Neuling <[email protected]> | 2019-06-20 16:00:40 +1000 |
---|---|---|
committer | Michael Ellerman <[email protected]> | 2019-07-03 15:19:36 +1000 |
commit | 3fefd1cd95df04da67c83c1cb93b663f04b3324f (patch) | |
tree | 1016f43d2c65f708b433ac360add43c0a9564ee0 /lib/test_overflow.c | |
parent | 5636427d087a55842c1a199dfb839e6545d30e5d (diff) |
KVM: PPC: Book3S HV: Fix CR0 setting in TM emulation
When emulating tsr, treclaim and trechkpt, we incorrectly set CR0. The
code currently sets:
CR0 <- 00 || MSR[TS]
but according to the ISA it should be:
CR0 <- 0 || MSR[TS] || 0
This fixes the bit shift to put the bits in the correct location.
This is a data integrity issue as CR0 is corrupted.
Fixes: 4bb3c7a0208f ("KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9")
Cc: [email protected] # v4.17+
Tested-by: Suraj Jitindar Singh <[email protected]>
Signed-off-by: Michael Neuling <[email protected]>
Signed-off-by: Michael Ellerman <[email protected]>
Diffstat (limited to 'lib/test_overflow.c')
0 files changed, 0 insertions, 0 deletions