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| author | Paul Cercueil <[email protected]> | 2020-09-03 03:50:46 +0200 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2020-10-13 20:04:50 -0700 |
| commit | 3860dc599b7d3de869d9d7e2274d2ca8f1e2be86 (patch) | |
| tree | edf46c7e0b793b0d54983244794d7f6541c50bdb /lib/test_overflow.c | |
| parent | 21534fe39c494913849f3c46e41282b96bce7df6 (diff) | |
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
CLK_SET_RATE_GATE means that the clock must be gated when being
reclocked. This is not the case for the PLLs in Ingenic SoCs.
Signed-off-by: Paul Cercueil <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'lib/test_overflow.c')
0 files changed, 0 insertions, 0 deletions