clk: at91: sam9x60-pll: use frac when setting frequency

In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
the fractional part of PLL wasn't set on registers but it was
calculated and taken into account for determining div and mul
(see sam9x60_pll_get_best_div_mul()).

Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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