clk: qcom: dispcc: Update DP clk ops for phy design

The clk_rcg2_dp_determine_rate() function is used for the DP pixel clk.
This function should return the rate that can be achieved by the pixel
clk in 'struct clk_rate_request::rate' and match the logic similar to
what is seen in clk_rcg2_dp_set_rate(). But that isn't the case. Instead
the code merely bubbles the rate request up to the parent of the pixel
clk and doesn't try to do a rational approximation of the rate that
would be achieved by picking some m/n value for the RCG.

Let's change this logic so that we can assume the parent clk frequency
is fixed (it is because it's the VCO of the DP PLL that is configured
based on the link rate) and so that we can calculate what the m/n value
will be and adjust the req->rate appropriately.

Cc: Jeykumar Sankaran <[email protected]>
Cc: Chandan Uddaraju <[email protected]>
Cc: Vara Reddy <[email protected]>
Cc: Tanmay Shah <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Manu Gautam <[email protected]>
Cc: Sandeep Maheswaram <[email protected]>
Cc: Douglas Anderson <[email protected]>
Cc: Sean Paul <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Jonathan Marek <[email protected]>
Cc: Dmitry Baryshkov <[email protected]>
Cc: Rob Clark <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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