clk: keystone: sci-clk: fix parsing assigned-clock data during probe

The DT clock probe loop incorrectly terminates after processing "clocks"
only, fix this by re-starting the loop when all entries for current
DT property have been parsed.

Fixes: 8e48b33f9def ("clk: keystone: sci-clk: probe clocks from DT instead of firmware")
Reported-by: Peter Ujfalusi <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Santosh Shilimkar <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

0 files changed, 0 insertions, 0 deletions