diff options
| author | Peter Zijlstra <[email protected]> | 2019-06-13 15:43:19 +0200 |
|---|---|---|
| committer | Paul Burton <[email protected]> | 2019-08-31 11:05:17 +0100 |
| commit | 1c6c1ca318585f1096d4d04bc722297c85e9fb8a (patch) | |
| tree | a3337041a74654c9427dbbaeca1a7a917db996e3 /lib/test_overflow.c | |
| parent | dfc8d8de855d566eb83a27e58a69741de42a90da (diff) | |
mips/atomic: Fix loongson_llsc_mb() wreckage
The comment describing the loongson_llsc_mb() reorder case doesn't
make any sense what so ever. Instruction re-ordering is not an SMP
artifact, but rather a CPU local phenomenon. Clarify the comment by
explaining that these issue cause a coherence fail.
For the branch speculation case; if futex_atomic_cmpxchg_inatomic()
needs one at the bne branch target, then surely the normal
__cmpxch_asm() implementation does too. We cannot rely on the
barriers from cmpxchg() because cmpxchg_local() is implemented with
the same macro, and branch prediction and speculation are, too, CPU
local.
Fixes: e02e07e3127d ("MIPS: Loongson: Introduce and use loongson_llsc_mb()")
Cc: Huacai Chen <[email protected]>
Cc: Huang Pei <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Diffstat (limited to 'lib/test_overflow.c')
0 files changed, 0 insertions, 0 deletions