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| author | Garmin.Chang <[email protected]> | 2023-03-31 20:36:17 +0800 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2023-03-31 11:51:22 -0700 |
| commit | eb48cccda09597a309d66331744e1b8edf196a67 (patch) | |
| tree | 1ff4b63c9ef309fcc69f1c62423a8429541dbba8 /lib/test_fortify/write_overflow-strncpy-src.c | |
| parent | bb87c1109ce2f4c947b5b92a1f82ec75f8f969f8 (diff) | |
clk: mediatek: Add MT8188 vppsys0 clock support
Add MT8188 vppsys0 clock controller which provides clock gate
controller for Video Processor Pipe.
Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'lib/test_fortify/write_overflow-strncpy-src.c')
0 files changed, 0 insertions, 0 deletions