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author | Niravkumar L Rabara <[email protected]> | 2023-08-02 10:58:42 +0800 |
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committer | Dinh Nguyen <[email protected]> | 2023-08-08 06:32:34 -0500 |
commit | d5f0942b5066e28138476259d076e4d6c871da7d (patch) | |
tree | 68593ece6a1c23a4fa710dec235a37f93f0b50ef /lib/test_fortify/write_overflow-strncpy-src.c | |
parent | 2a29fe831f80f6d9187e49a272d795f3d1b54cdb (diff) |
dt-bindings: clock: add Intel Agilex5 clock manager
Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.
Signed-off-by: Teh Wen Ping <[email protected]>
Reviewed-by: Dinh Nguyen <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Niravkumar L Rabara <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>
Diffstat (limited to 'lib/test_fortify/write_overflow-strncpy-src.c')
0 files changed, 0 insertions, 0 deletions