diff options
| author | Xingyu Wu <[email protected]> | 2023-07-17 10:30:34 +0800 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2023-07-19 18:07:48 +0100 |
| commit | bd348ca24d81cca2a27f8ffa12adc8f30f184275 (patch) | |
| tree | c70d6233857bc91f11f4b3ef10cabb76bcea8e28 /lib/test_fortify/write_overflow-strncpy-src.c | |
| parent | 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5 (diff) | |
dt-bindings: clock: Add StarFive JH7110 PLL clock generator
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Diffstat (limited to 'lib/test_fortify/write_overflow-strncpy-src.c')
0 files changed, 0 insertions, 0 deletions