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| author | Pierre-Louis Bossart <[email protected]> | 2024-06-03 15:02:40 +0800 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2024-06-03 17:41:11 +0530 |
| commit | 9b5fd115e7d5a98b82054cff5c96f6768ee06845 (patch) | |
| tree | 93eb1dbd77743a3834aa9facbc4573b475d3d94c /lib/test_fortify/write_overflow-strncpy-src.c | |
| parent | a5b7365f28c191df6b93f60942d2b9a9fe71746c (diff) | |
soundwire: intel_ace2.x: add AC timing extensions for PantherLake
The ACE3 IP used in PantherLake exposes new bitfields in the ACTMCTL
register to better control clocks/delays. These bitfields were
reserved/zero in the ACE2.x IP, to simplify the integration the new
bifields are added unconditionally. The behavior will only be impacted
when the firmware exposes DSD properties to set non-zero values.
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Péter Ujfalusi <[email protected]>
Reviewed-by: Ranjani Sridharan <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'lib/test_fortify/write_overflow-strncpy-src.c')
0 files changed, 0 insertions, 0 deletions