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| author | Ville Syrjälä <[email protected]> | 2024-04-17 18:12:11 +0300 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2024-04-19 19:45:42 +0300 |
| commit | 8034945d1a5e56f7eb1885cdd21801f93153b5a6 (patch) | |
| tree | bee5cbf67c321bba39036cfa72d79119861253cd /lib/test_fortify/write_overflow-strncpy-src.c | |
| parent | 8221a6229a8509bf0e51046d43dd8d3d85cdf8dd (diff) | |
drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk
Add consistent definitions for the per-lane PHY TX registers
on bxt/glk. The current situation is a slight mess with some
registers having a LN0 define, while others have a parametrized
per-lane definition.
v2: Adjust gvt accordingly
Reviewed-by: Jani Nikula <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'lib/test_fortify/write_overflow-strncpy-src.c')
0 files changed, 0 insertions, 0 deletions