diff options
| author | Emil Renner Berthing <[email protected]> | 2023-04-01 19:19:13 +0800 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2023-04-05 15:43:15 +0100 |
| commit | 7fce1e39f01900a294cd2c456c77f3e2512e0634 (patch) | |
| tree | 85f891edba674cfb16bf38d621b4bd19e8f1b390 /lib/test_fortify/write_overflow-strncpy-src.c | |
| parent | eeac8ede17557680855031c6f305ece2378af326 (diff) | |
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
Add bindings for the system clock and reset generator (SYSCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Diffstat (limited to 'lib/test_fortify/write_overflow-strncpy-src.c')
0 files changed, 0 insertions, 0 deletions