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| author | Khaled Almahallawy <[email protected]> | 2023-10-04 17:13:10 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <[email protected]> | 2023-10-17 22:08:49 -0400 |
| commit | 5e4c16fe08c8b894b258f4110349dc9b642669f9 (patch) | |
| tree | 2d4dc808a0e91d2491b6c5e17a8018ac1d2051d2 /lib/test_fortify/write_overflow-strncpy-src.c | |
| parent | 58720809f52779dc0f08e53e54b014209d13eebb (diff) | |
drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes Owned
Currently, with MFD/pin assignment D, the driver clears the pipe reset bit
of lane 1 which is not owned by display. This causes the display
to block S0iX.
By not clearing this bit for lane 1 and keeping whatever default, S0ix
started to work. This is already what the driver does at the end
of the phy lane reset sequence (Step#8)
Bspec: 65451
Fixes: 619a06dba6fa ("drm/i915/mtl: Reset only one lane in case of MFD")
Cc: Mika Kahola <[email protected]>
Cc: Gustavo Sousa <[email protected]>
Signed-off-by: Khaled Almahallawy <[email protected]>
Reviewed-by: Gustavo Sousa <[email protected]>
Signed-off-by: Radhakrishna Sripada <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit 4a07f063d20c46524f00976f4537de72d9f31c4e)
Signed-off-by: Rodrigo Vivi <[email protected]>
Diffstat (limited to 'lib/test_fortify/write_overflow-strncpy-src.c')
0 files changed, 0 insertions, 0 deletions