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author | Yassine Oudjana <[email protected]> | 2022-07-14 13:03:46 +0300 |
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committer | Bjorn Andersson <[email protected]> | 2022-09-26 11:12:44 -0500 |
commit | da5daae8b412c922e08f86979e84ea80b60092a1 (patch) | |
tree | 89077fc0ea2c61432dfde2961cc6b64e534c8bdf /lib/test_fortify/write_overflow-strlcpy.c | |
parent | b4feed4a3d0a6b8cef4a574a9df707c556928ec2 (diff) |
clk: qcom: msm8996-cpu: Use parent_data/_hws for all clocks
Replace parent_names in PLLs, secondary muxes and primary muxes with
parent_data. For primary muxes there were never any *cl_pll_acd clocks,
so instead of adding them, put the primary PLLs in both PLL_INDEX and
ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when
setting parent since we always want ACD when using the primary PLLs.
Signed-off-by: Yassine Oudjana <[email protected]>
[DB: switch to parent_hws for pmux clocks]
Signed-off-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'lib/test_fortify/write_overflow-strlcpy.c')
0 files changed, 0 insertions, 0 deletions