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authorChristian Marangi <[email protected]>2022-08-19 00:06:20 +0200
committerBjorn Andersson <[email protected]>2022-09-26 21:40:10 -0500
commitc5d2c96b3a7bd8987fad9957510034130037fccf (patch)
tree731c3eb15412144a17c14f74bb8f88b0c296941a /lib/test_fortify/write_overflow-strlcpy.c
parent18f6e9cd7fa3ef6a6dcb10d3fe357afaa52bd216 (diff)
clk: qcom: clk-rcg2: add rcg2 mux ops
An RCG may act as a mux that switch between 2 parents. This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds the CPU cluster clock just switches between XO and the PLL that feeds it. Add the required ops to add support for this special configuration and use the generic mux function to determine the rate. This way we dont have to keep a essentially dummy frequency table to use RCG2 as a mux. Signed-off-by: Christian Marangi <[email protected]> Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'lib/test_fortify/write_overflow-strlcpy.c')
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