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| author | Chanho Park <[email protected]> | 2022-06-29 19:23:02 +0900 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2022-06-29 12:37:07 +0100 |
| commit | bfcd27dcb7b93bd1f3b89d03d8b90207876d635f (patch) | |
| tree | 29fd3cf7ef74d0107b058db44394b8fd1ae8c6db /lib/test_fortify/write_overflow-strlcpy.c | |
| parent | ffb7bcd3b27e86fa7bdbabf4488060064ec9d00d (diff) | |
spi: s3c64xx: support custom value of internal clock divider
Modern exynos SoCs such as Exynos Auto v9 have different internal clock
divider, for example "4". To support this internal value, this adds
clk_div of the s3c64xx_spi_port_config and assign "2" as the default
value to existing s3c64xx_spi_port_config.
Signed-off-by: Chanho Park <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'lib/test_fortify/write_overflow-strlcpy.c')
0 files changed, 0 insertions, 0 deletions