diff options
| author | Prasad Malisetty <pmaliset@codeaurora.org> | 2021-10-07 23:18:43 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2021-10-14 16:54:27 -0500 |
| commit | aa9c0df98c2920f7176b001737546c6595f594a4 (patch) | |
| tree | 7babf150fb4564ddaf29f8aa39b4c5732afd72c2 /lib/test_fortify/write_overflow-memset.c | |
| parent | b89ff410253d7468f84720d2d5c2bb0bafedf3bd (diff) | |
PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280
On the SC7280, the clock source for gcc_pcie_1_pipe_clk_src must be the
TCXO while gdsc is enabled. After PHY init successful clock source should
switch to pipe clock for gcc_pcie_1_pipe_clk_src.
Link: https://lore.kernel.org/r/1633628923-25047-6-git-send-email-pmaliset@codeaurora.org
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Diffstat (limited to 'lib/test_fortify/write_overflow-memset.c')
0 files changed, 0 insertions, 0 deletions