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author | Dmitry Baryshkov <[email protected]> | 2022-03-23 11:50:06 +0300 |
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committer | Bjorn Andersson <[email protected]> | 2022-04-12 13:32:53 -0500 |
commit | e9a4c7f667ed16a95da0e9d68cc88b381dcd99f9 (patch) | |
tree | 42d564da110e5fa906f4ccd552799677e59ebb4f /lib/test_fortify/write_overflow-memcpy.c | |
parent | 3123109284176b1532874591f7c81f3837bbdc17 (diff) |
clk: qcom: regmap-mux: add pipe clk implementation
On recent Qualcomm platforms the QMP PIPE clocks feed into a set of
muxes which must be parked to the "safe" source (bi_tcxo) when
corresponding GDSC is turned off and on again. Currently this is
handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src
clock. However the same code sequence should be applied in the
pcie-qcom endpoint, USB3 and UFS drivers.
Rather than copying this sequence over and over again, follow the
example of clk_rcg2_shared_ops and implement this parking in the
enable() and disable() clock operations. As we are changing the parent
behind the back of the clock framework, also implement custom
set_parent() and get_parent() operations behaving accroding to the clock
framework expectations (cache the new parent if the clock is in disabled
state, return cached parent).
Signed-off-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'lib/test_fortify/write_overflow-memcpy.c')
0 files changed, 0 insertions, 0 deletions