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| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2023-03-15 12:38:00 +0530 |
|---|---|---|
| committer | Lorenzo Pieralisi <lpieralisi@kernel.org> | 2023-05-08 09:16:57 +0200 |
| commit | 0e12f830236928b6fadf40d917a7527f0a048d2f (patch) | |
| tree | 366b90c75126434d7825bf28b0eb03e9f25c2fa0 /lib/test-string_helpers.c | |
| parent | ac9a78681b921877518763ba0e89202254349d1b (diff) | |
PCI: cadence: Fix Gen2 Link Retraining process
The Link Retraining process is initiated to account for the Gen2 defect in
the Cadence PCIe controller in J721E SoC. The errata corresponding to this
is i2085, documented at:
https://www.ti.com/lit/er/sprz455c/sprz455c.pdf
The existing workaround implemented for the errata waits for the Data Link
initialization to complete and assumes that the link retraining process
at the Physical Layer has completed. However, it is possible that the
Physical Layer training might be ongoing as indicated by the
PCI_EXP_LNKSTA_LT bit in the PCI_EXP_LNKSTA register.
Fix the existing workaround, to ensure that the Physical Layer training
has also completed, in addition to the Data Link initialization.
Link: https://lore.kernel.org/r/20230315070800.1615527-1-s-vadapalli@ti.com
Fixes: 4740b969aaf5 ("PCI: cadence: Retrain Link to work around Gen2 training defect")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'lib/test-string_helpers.c')
0 files changed, 0 insertions, 0 deletions