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| author | Jamie Gibbons <jamie.gibbons@microchip.com> | 2024-03-27 12:24:37 +0000 |
|---|---|---|
| committer | Bartosz Golaszewski <bartosz.golaszewski@linaro.org> | 2024-03-29 13:21:30 +0100 |
| commit | 6e12a52c1459b791f27396a9b656b92aaa600065 (patch) | |
| tree | 9992850252fd3bfb01f8029fa1c9d6b1f01f8918 /lib/raid6/recov_loongarch_simd.c | |
| parent | 4cece764965020c22cff7665b18a012006359095 (diff) | |
dt-bindings: gpio: mpfs: add coreGPIO support
The GPIO controllers on PolarFire SoC were based on the "soft" IP
CoreGPIO, but the inp/outp registers are at different offsets. Add
compatible to allow for support of both sets of offsets. The soft
core will not always have interrupts wired up, so only enforce them for
the "hard" core on PolarFire SoC.
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Diffstat (limited to 'lib/raid6/recov_loongarch_simd.c')
0 files changed, 0 insertions, 0 deletions