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authorFinley Xiao <[email protected]>2019-09-17 10:19:00 +0200
committerHeiko Stuebner <[email protected]>2019-11-05 20:53:30 +0100
commite40781098f56dab52e92b7651d87b38805536d28 (patch)
treeb73483ceda7fad8ef883368561207beebedcb127 /lib/mpi/mpiutil.c
parent762539d6999caa1d9a916a4ce72004977b2433cf (diff)
clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc
Some IPs, such as NAND, EMMC, SDIO and SDMMC need clock of 50% duty cycle, divfree50 can generate clock of 50% duty cycle even in odd value divisor. Signed-off-by: Finley Xiao <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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