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authorAtish Patra <[email protected]>2020-04-02 18:46:09 -0700
committerMarc Zyngier <[email protected]>2020-04-17 08:59:28 +0100
commitd727be7bbf7b68ccc18a3278469325d8f486d75b (patch)
tree351489f538a56d684e7f462da3026aee5a4c8710 /lib/mpi/mpicoder.c
parent3688b0db5c331f4ec3fa5eb9f670a4b04f530700 (diff)
irqchip/sifive-plic: Fix maximum priority threshold value
As per the PLIC specification, maximum priority threshold value is 0x7 not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed, there may be some implementation which checks the upper bound resulting in an illegal access. Fixes: ccbe80bad571 ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline") Signed-off-by: Atish Patra <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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