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authorKrish Sadhukhan <krish.sadhukhan@oracle.com>2020-09-17 21:20:36 +0000
committerBorislav Petkov <bp@suse.de>2020-09-18 10:46:41 +0200
commit5866e9205b47a983a77ebc8654949f696342f2ab (patch)
treeabdb11c74714c51902b260990139d5536cf0df02 /lib/mpi/mpicoder.c
parent33b4711df4c1b3aec7c267c60fc24abccfadd40c (diff)
x86/cpu: Add hardware-enforced cache coherency as a CPUID feature
In some hardware implementations, coherency between the encrypted and unencrypted mappings of the same physical page is enforced. In such a system, it is not required for software to flush the page from all CPU caches in the system prior to changing the value of the C-bit for a page. This hardware- enforced cache coherency is indicated by EAX[10] in CPUID leaf 0x8000001f. [ bp: Use one of the free slots in word 3. ] Suggested-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200917212038.5090-2-krish.sadhukhan@oracle.com
Diffstat (limited to 'lib/mpi/mpicoder.c')
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