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| author | Chaitanya Kumar Borah <[email protected]> | 2023-05-29 11:37:47 +0530 |
|---|---|---|
| committer | Joonas Lahtinen <[email protected]> | 2023-06-05 14:19:32 +0300 |
| commit | cb2e701305f4ffe3a107c1d97f8588b4ed48ccb3 (patch) | |
| tree | cbd5a83125234df207b1874a0f465ed2c37cbceb /lib/mpi/mpi-sub-ui.c | |
| parent | 40023959dbab3c6ad56fa7213770e63d197b69fb (diff) | |
drm/i915/display: Set correct voltage level for 480MHz CDCLK
According to Bspec, the voltage level for 480MHz is to be set as 1
instead of 2.
BSpec: 49208
Fixes: 06f1b06dc5b7 ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")
v2: rebase
Signed-off-by: Chaitanya Kumar Borah <[email protected]>
Reviewed-by: Mika Kahola <[email protected]>
Signed-off-by: Matt Roper <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit 5a3c46b809d09f8ef59e2fbf2463b1c102aecbaa)
Signed-off-by: Joonas Lahtinen <[email protected]>
Diffstat (limited to 'lib/mpi/mpi-sub-ui.c')
0 files changed, 0 insertions, 0 deletions