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| author | Selvam Sathappan Periakaruppan <[email protected]> | 2021-05-05 12:18:32 +0300 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2021-08-05 10:27:34 -0500 |
| commit | 095bbdd9a5c302ca4636c8fc92216ac008f46491 (patch) | |
| tree | 826867f41cb7d8a81de1f7089b2ab2c509bc2ed1 /lib/mpi/mpi-sub-ui.c | |
| parent | f70c6dc013c1842b0ca640926cf74e7b99cec33d (diff) | |
arm64: dts: qcom: ipq6018: Add pcie support
ipq6018 has 1 pcie gen3 port. This patch adds the support for the same.
The GICv2m reg property value is a guess based on similar SoCs
description in downstream Codeaurora kernel. It appears to work.
Signed-off-by: Selvam Sathappan Periakaruppan <[email protected]>
[baruch: adjust #address-cells/#size-cells; drop unsupported property;
increase parf registers size]
Signed-off-by: Baruch Siach <[email protected]>
Link: https://lore.kernel.org/r/0f733656666fa6adaa8e196419ebcfd04677d173.1620203062.git.baruch@tkos.co.il
Signed-off-by: Bjorn Andersson <[email protected]>
Diffstat (limited to 'lib/mpi/mpi-sub-ui.c')
0 files changed, 0 insertions, 0 deletions