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authorMagnus Damm <[email protected]>2019-08-20 21:35:46 +0900
committerDaniel Lezcano <[email protected]>2019-08-27 00:31:39 +0200
commit1be8c9fd2ac9ad730cf537b8909f66c357866c5d (patch)
treeae380b4907c20159b2a3198a5f2c3b1fa6bc9bac /lib/mpi/mpi-mul.c
parent53933bc3a69e0f07a1af2fea16fda9c816ffcf87 (diff)
dt-bindings: timer: renesas, cmt: Update R-Car Gen3 CMT1 usage
The R-Car Gen3 SoCs so far come with a total for 4 on-chip CMT devices: - CMT0 - CMT1 - CMT2 - CMT3 CMT0 includes two rather basic 32-bit timer channels. The rest of the on-chip CMT devices support 48-bit counters and have 8 channels each. Based on the data sheet information "CMT2/3 are exactly same as CMT1" it seems that CMT2 and CMT3 now use the CMT1 compat string in the DTSI. Clarify this in the DT binding documentation by describing R-Car Gen3 and RZ/G2 CMT1 as "48-bit CMT devices". Signed-off-by: Magnus Damm <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
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