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authorJean-Philippe Brucker <[email protected]>2022-09-16 14:31:47 +0100
committerJoerg Roedel <[email protected]>2022-09-26 14:05:58 +0200
commitd2f2f1d10ccdb96aeea38c5ec647679fcc093b84 (patch)
treeddccaddc3d45261b6042391980e335639a3be634 /lib/mpi/mpi-mod.c
parent7e18e42e4b280c85b76967a9106a13ca61c16179 (diff)
dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names
The QEMU devicetree uses a different order for SMMUv3 interrupt names, and there isn't a good reason for enforcing a specific order. Since all interrupt lines are optional, operating systems should not expect a fixed interrupt array layout; they should instead match each interrupt to its name individually. Besides, as a result of commit e4783856a2e8 ("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync" and "priq" are already permutable. Relax the interrupt-names array entirely by allowing any permutation, incidentally making the schema more readable. Note that dt-validate won't allow duplicate names here so we don't need to specify maxItems or add additional checks, it's quite neat. Signed-off-by: Jean-Philippe Brucker <[email protected]> Acked-by: Will Deacon <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
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