diff options
| author | Qiqi Zhang <[email protected]> | 2022-11-25 18:45:58 +0800 |
|---|---|---|
| committer | Douglas Anderson <[email protected]> | 2022-11-30 06:40:20 -0800 |
| commit | 8c115864501fc09932cdfec53d9ec1cde82b4a28 (patch) | |
| tree | e6a9002a4105794532bcac4ccfab5f0ecff42c1a /lib/mpi/mpi-mod.c | |
| parent | ed14d225cc7c842f6d4d5a3009f71a44f5852d09 (diff) | |
drm/bridge: ti-sn65dsi86: Fix output polarity setting bug
According to the description in ti-sn65dsi86's datasheet:
CHA_HSYNC_POLARITY:
0 = Active High Pulse. Synchronization signal is high for the sync
pulse width. (default)
1 = Active Low Pulse. Synchronization signal is low for the sync
pulse width.
CHA_VSYNC_POLARITY:
0 = Active High Pulse. Synchronization signal is high for the sync
pulse width. (Default)
1 = Active Low Pulse. Synchronization signal is low for the sync
pulse width.
We should only set these bits when the polarity is negative.
Fixes: a095f15c00e2 ("drm/bridge: add support for sn65dsi86 bridge driver")
Signed-off-by: Qiqi Zhang <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Tested-by: Douglas Anderson <[email protected]>
Reviewed-by: Tomi Valkeinen <[email protected]>
Signed-off-by: Douglas Anderson <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'lib/mpi/mpi-mod.c')
0 files changed, 0 insertions, 0 deletions