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author | Biju Das <[email protected]> | 2023-03-30 12:16:30 +0100 |
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committer | Lee Jones <[email protected]> | 2023-04-26 11:40:35 +0100 |
commit | 0be8907359df4c62319f5cb2c6981ff0d9ebf35a (patch) | |
tree | 2d03f6a7a0213fe1d98cffd7e8d694d2815ca3b5 /lib/mpi/mpi-mod.c | |
parent | 7bb985ac03c4a91d185c006f68c4fadfb71e1cca (diff) |
counter: Add Renesas RZ/G2L MTU3a counter driver
Add RZ/G2L MTU3a counter driver. This IP supports the following
phase counting modes on MTU1 and MTU2 channels
1) 16-bit phase counting modes on MTU1 and MTU2 channels.
2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels.
This patch adds 3 counter value channels.
count0: 16-bit phase counter value channel on MTU1
count1: 16-bit phase counter value channel on MTU2
count2: 32-bit phase counter value channel by cascading
MTU1 and MTU2 channels.
The external input phase clock pin for the counter value channels
are as follows:
count0: "MTCLKA-MTCLKB"
count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD"
count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD"
Use the sysfs variable "external_input_phase_clock_select" to select the
external input phase clock pin and "cascade_counts_enable" to enable/
disable cascading of channels.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: William Breathitt Gray <[email protected]>
Acked-by: William Breathitt Gray <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'lib/mpi/mpi-mod.c')
0 files changed, 0 insertions, 0 deletions