ARM: dts: qcom: Add nodes for SMP boot in IPQ40xx

Add missing nodes and properties to enable SMP
support on IPQ40xx devices.

Booting without "saw_l2" node:

[    0.001400] CPU: Testing write buffer coherency: ok
[    0.001856] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.060163] Setting up static identity map for 0x80300000 - 0x80300060
[    0.080140] rcu: Hierarchical SRCU implementation.
[    0.120258] smp: Bringing up secondary CPUs ...
[    0.200540] CPU1: failed to boot: -19
[    0.280689] CPU2: failed to boot: -19
[    0.360874] CPU3: failed to boot: -19
[    0.360966] smp: Brought up 1 node, 1 CPU
[    0.360979] SMP: Total of 1 processors activated (96.00 BogoMIPS).
[    0.360988] CPU: All CPU(s) started in SVC mode.

Then, booting with "saw_l2" node present (this patch applied):

[    0.001450] CPU: Testing write buffer coherency: ok
[    0.001904] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.060161] Setting up static identity map for 0x80300000 - 0x80300060
[    0.080137] rcu: Hierarchical SRCU implementation.
[    0.120252] smp: Bringing up secondary CPUs ...
[    0.200958] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.281091] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
[    0.361264] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
[    0.361430] smp: Brought up 1 node, 4 CPUs
[    0.361460] SMP: Total of 4 processors activated (384.00 BogoMIPS).
[    0.361469] CPU: All CPU(s) started in SVC mode.

Signed-off-by: Damir Franusic <[email protected]>
Cc: Luka Perkov <[email protected]>
Cc: Robert Marko <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

0 files changed, 0 insertions, 0 deletions